1. Field
The present invention relates to a method of manufacturing a semiconductor device that includes a drift layer formed of an alternating conductivity type layer including an n-type column and a p-type column, both extending in perpendicular to the major surface of a semiconductor substrate. The n-type column and the p-type column are arranged alternately and repeatedly in parallel to the major surface of a semiconductor substrate such that the n-type column and the p-type column are adjoining to each other. Hereinafter, “super-junction” refers to the alternating conductivity type layer, and “super-junction semiconductor device” refers to the semiconductor device including an alternating conductivity type layer.
2. Description of the Related Art
A super-junction MOSFET (hereinafter referred to as a “SJ-MOSFET”) that is a vertical power MOSFET including a drift layer provided with a super-junction structure is one known super-junction semiconductor device.
In FIG. 6, a cross sectional view of a SJ-MOSFET, the drift layer thereof provided with a super-junction structure is formed of alternating conductivity type layer 104 including n-type column 101 and p-type column 103, both extending in perpendicular to the major surface of heavily doped n+ silicon semiconductor substrate 100. The n-type column 101 and p-type column 103 are arranged alternately and repeatedly in parallel to the major surface of heavily doped n+ silicon semiconductor substrate 100. The SJ-MOSFET also includes p-type base region 105, n-type source region 106, gate insulator film 107, polysilicon gate electrode 108, interlayer insulator film 109 made from boro-phosphosilicate glass (BPSG), source electrode 110, surface protector film 111, and drain electrode 112.
Even if the impurity concentrations in the p-type and n-type columns are set to be higher than the impurity concentrations in the usual power semiconductor device of the same breakdown voltage class, depletion layers expand from the pn-junction between the p-type and n-type columns to both sides in the OFF-state of the device, depleting the p-type and n-type columns at a low electric field strength. Therefore, it is possible to provide the super-junction semiconductor device with a higher breakdown voltage.
As a result, the super-junction semiconductor device exhibits excellent semiconductor device performances. In detail, the super-junction semiconductor device facilitates reducing the ON-state resistance, that is in the tradeoff relation against the breakdown voltage, to a value not only low enough to transcend the tradeoff relation but also low enough to transcend the theoretical limit of the material.
For manufacturing the super-junction structure, the method combining a multi-step epitaxial growth and ion implantation (hereinafter referred to simply as the “multi-step epitaxial growth method”) has been developed and the SJ-MOSFETs having the super-junction structure formed by the multi-step epitaxial growth method are manufactured.
In detail, an n− layer (not shown) that will work as a buffer layer is formed on heavily doped n+ silicon semiconductor substrate 100 in FIG. 6. Then, a trench having a side wall perpendicular to the substrate surface is formed by anisotropic dry-etching and such an etching technique as an alignment mark used for positioning in the subsequent steps in the section on the n− layer surface (not shown), in which a scribe line is planned.
Then, a non-doped epitaxial layer is grown, an n-type ion-implanted region is formed, a photoresist is patterned using the alignment mark, and a p-type ion-implanted region is formed by selective ion implantation through the photoresist opening. The step of growing a non-doped epitaxial layer, the step of forming an n-type ion-implanted region, and the step of forming a p-type ion-implanted region are repeated a predetermined number of times such that an upper p-type ion-implanted region is positioned on the lower p-type ion-implanted region.
As described above, the multi-step epitaxial growth method is a method that repeats the steps of growing a non-doped epitaxial layer, patterning a resist, and implanting impurity ions to pile up p-type ion-implanted regions and n-type ion-implanted regions in the same respective sites. Then, the multi-step epitaxial growth method thermally drives the p-type and n-type ion-implanted regions to expand and connects the p-type ion-implanted regions and the n-type ion-implanted regions in perpendicular to the substrate major surface, for forming an alternating conductivity type layer.
It is important for the multi-step epitaxial growth method to position the ion-implanted region of a conductivity type in the upper layer exactly on the ion-implanted region of the same conductivity type in the lower layer. Since the alignment mark described above is necessary as a reference for the exact positioning, it is required for the alignment mark to have a clear shape.
In growing an epitaxial layer on the silicon wafer 120, in which a trench-shaped alignment mark is formed, the trench pattern for the alignment mark will be deformed if the growth rate is too high. The trench pattern for the alignment mark is deformed, for example, as follows. As silicon epitaxial layer 122 is grown on the alignment mark shaped with trench 121 (the cross sectional view thereof is shown in FIG. 2(a)), the alignment mark is deformed, as schematically described in FIG. 2(b), such that what is left is not any horizontally flat section, left but a triangular cross section or a curved cross section (not shown) caused in the alignment mark. The alignment mark's lack of any horizontally flat section tends to be caused when the silicon epitaxial layer 122 growth rate is high.
If a pattern similar to trench 121, formed before silicon epitaxial layer 122 is grown, is not formed in the silicon epitaxial layer 122 surface but the deformed pattern as described above is caused in silicon epitaxial layer 122, it will be difficult to automatically detect the alignment mark with a detector and the alignment will be conducted hardly or an alignment deviation will be caused.
If an alignment deviation is caused, the ion-implanted regions of the same conductivity type in the upper and lower layers will deviate easily from each other, the columnar regions in the alternating conductivity type layer will be extended neither in perpendicular to the substrate surface nor straightly, and the semiconductor device performances will be impaired.
In the multi-step epitaxial growth, an epitaxial layer is grown repeatedly many times and the treatment steps also tend to be repeated many times. For reducing the treatment steps, it is preferable to form an alignment mark in a wafer, to grow an epitaxial layer on the wafer with the alignment mark formed therein and to conduct next patterning using the alignment mark transferred to the epitaxial layer without correction. It is also desirable for the epitaxial growth rate to be fast as much as possible from the view point of efficient manufacture. If an alignment mark pattern deformation after the epitaxial layer growth is expected, it will be necessary to correct the alignment mark size appropriately. If an alignment mark pattern deformation too large to correct is caused, it will be necessary to add the step of forming an alignment mark again. Alignment mark size correction or alignment mark reformation is not preferable, since manufacturing costs soar.
In view of such problems caused by the multi-step epitaxial growth method, Japanese Unexamined Patent Application Publication No. Hei. 5 (1993)-343319 proposes the following countermeasures. An epitaxial layer is grown multiple times on a heavily doped n+ silicon semiconductor substrate. As for the alignment marks formed in the surface portions of the respective epitaxial layers for patterning the ion-implanted regions of a conductivity type and for piling up the ion-implanted regions of the same conductivity type exactly, a new alignment mark used for patterning the second epitaxial layer surface is formed at a position different from the position at which the alignment mark used for patterning the first epitaxial layer surface is formed. The new alignment mark improves the accuracy of aligning the ion-implanted regions of the same conductivity type rather than using the alignment mark transferred to the second epitaxial layer from the first epitaxial layer.
JP No. Hei. 5 (1993)-343319 also describes an etching method for sharpening the boundary of the transferred alignment mark blunted by every epitaxial layer growth to be clear enough for a next mask alignment.
Japanese Unexamined Patent Application Publication No. 2008-130919 describes the preferable use of KOH for an etchant that corrects the blunted alignment mark boundary to be sharp.
Japanese Unexamined Patent Application Publication No. 2009-188118 discloses that it is effective to set the alignment mark pitch to be from 8 μm to 10 μm for securing an automatic alignment mark detection, when an epitaxial layer of 20 μm in thickness is grown. In one of its drawings, an alignment mark of 4 μm×4 μm size is described at a pitch of 10 μm. The drawing indicates that the mesa region is 6 μm in width.
For the manufacture of a super-junction structure by the multi-step epitaxial growth method, it is important to prevent the ion-implanted region of a conductivity type in the upper epitaxial layer from deviating from the ion-implanted region of the same conductivity type in the lower epitaxial layer. However, the alignment mark shape deforms more depending on the epitaxial growth conditions as more epitaxial layers are deposited, resulting in a deformation too large to detect the alignment mark exactly. If the alignment mark is not detected exactly, it will be impossible to align the ion-implanted region of a conductivity type in the upper epitaxial layer on the ion-implanted region of the same conductivity type in the lower epitaxial layer properly.
In the situation described above, it will be possible to detect the alignment mark and to align the ion-implanted region in the upper epitaxial layer on the ion-implanted region in the lower epitaxial layer properly, if the deformed alignment mark size is corrected as described in JP No. Hei. 5 (1993)-343319. However, it becomes necessary to add the step of correcting the deformed alignment mark size.
It is possible to sharpen the blunted alignment mark boundary by the etching with KOH so that an alignment may be successful. It is also possible to form a new alignment mark so that an alignment may be successful. However, it will be necessary to add the step of new resist patterning or to add the step of etching to form a trench, if any of the methods described above is employed.
If the epitaxial layer growth rate is made to be low, the alignment mark will not be blunted nor deformed so much. However, since the epitaxial layer growth is repeated more times to obtain a higher breakdown voltage, the lower epitaxial growth rate impairs the manufacturing efficiency. Therefore, the lower epitaxial growth rate is not preferable.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a method of manufacturing a super-junction semiconductor device that facilitates reducing the additional manufacturing steps. It would be further desirable to provide a method of manufacturing a super-junction semiconductor device that facilitates suppressing the shape change caused in the transferred alignment mark to be small enough, even if the epitaxial layer growth rate is high, such that the transferred alignment mark is detectable, when the alignment mark in the lower epitaxial layer is transferred to the upper epitaxial layer surface.